
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
15
IDT5V49EE902
REV P 092412
I2C Bus DC Characteristics
I2C Bus AC Characteristics for Standard Mode
Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the VIH(MIN)
of the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Level
0.7xVDD
V
VIL
Input LOW Level
0.3xVDD
V
VHYS
Hysteresis of Inputs
0.05xVDD
V
IIN
Input Leakage Current
±1.0
A
VOL
Output LOW Voltage
IOL = 3 mA
0.4
V
Symbol
Parameter
Min
Typ
Max
Unit
FSCLK
Serial Clock Frequency (SCL)
0
100
kHz
tBUF
Bus free time between STOP and START
4.7
s
tSU:START Setup Time, START
4.7
s
tHD:START Hold Time, START
4
s
tSU:DATA
Setup Time, data input (SDA)
250
ns
tHD:DATA
Hold Time, data input (SDA) 1
0s
tOVD
Output data valid from clock
3.45
s
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDAT, SCLK)
1000
ns
tF
Fall Time, data and clock (SDAT, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
s
tLOW
LOW Time, clock (SCLK)
4.7
s
tSU:STOP
Setup Time, STOP
4
s